{"id":5471,"date":"2024-03-22T16:02:03","date_gmt":"2024-03-22T07:02:03","guid":{"rendered":"https:\/\/shinko-sj.co.jp\/wp2024\/?page_id=5471"},"modified":"2025-02-12T03:45:31","modified_gmt":"2025-02-11T18:45:31","slug":"seminar","status":"publish","type":"page","link":"https:\/\/shinko-sj.co.jp\/en\/seminar\/","title":{"rendered":"External seminar information"},"content":{"rendered":"

External Seminars<\/h2>\n\n\n\n

We will provide you with information on external seminars held by manufacturers that we deal with. We provide useful information for hardware and software developers, so please feel free to register and participate.<\/p>\n\n\n\n

Seminar Overview <\/p>\n\n\n\n

For customers who want to obtain product information, select products, or learn development methods, we will solve your development problems through on-site training and online seminars.<\/strong><\/p>\n\n\n\n

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Get the latest product information<\/h4>\n\n\n\n

We will deliver the latest information on product features, programming methods, etc.<\/p>\n<\/div>\n\n\n\n

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Specific and easy to understand<\/strong><\/h4>\n\n\n\n

Learn specific development techniques at seminars using evaluation boards and various tools<\/p>\n<\/div>\n\n\n\n

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Find hints for development and evaluation<\/h4>\n\n\n\n

Through training, you can learn efficient design and debugging methods.<\/p>\n<\/div>\n<\/div>\n\n\n\n

Upcoming Events<\/h3>\n\n\n\n
\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n
title<\/th>\n Company Name<\/th>\n category<\/th>\n Date<\/th>\n Closing date<\/th>\n Reception status<\/th>\n <\/tr>\n\n \n\n\n
\n Armadillo Base OS Basic Seminar <\/td>\n \n
\n \"\u30a2\u30c3\u30c8\u30de\u30fc\u30af\u30c6\u30af\u30ce\"\n <\/div>\n \n <\/td>\n
Embedded
CPU Board<\/td>\n 		Manufacturer
On the homepage
Please check.<\/td>\n 		<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n
\n Getting started with Kria KV260 <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n June 30th (Tuesday)<\/td>\n June 19<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n
\n Migrating to the Vitis Unified IDE<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Wednesday, June 24th<\/td>\n June 15<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Debugging with Vivado Logic Analyzer: Basics<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n June 23rd (Tuesday)<\/td>\n June 12<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Software and hardware design and implementation seminar<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n June 16th (Tuesday)<\/td>\n June 5th<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Timing Closure Techniques Part 2<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n June 16th (Tuesday)<\/td>\n June 5th<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Timing Closure Techniques Part 1<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Monday, June 15th<\/td>\n June 4th<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Embedded Linux Development with Yocto<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Friday, June 12th<\/td>\n June 3<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n [VHDL] Beginner's guide to RTL design using Xilinx\/Vivado tools<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Thursday, June 11th -
Friday, June 12th<\/td>\n 		June 2<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Vitis Model Composer<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Thursday, June 11th -
Friday, June 12th<\/td>\n 		June 2<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Verification with SystemVerilog<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n June 9th (Tuesday) -
Wednesday, June 10th<\/td>\n 		May 29<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Zynq UltraScale+ MPSoC Boot and Platform Management<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Thursday, June 4th -
Friday, June 5th<\/td>\n 		May 26<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n OS and Hypervisors in Adaptive SoCs<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n June 2nd (Tuesday) -
Wednesday, June 3rd<\/td>\n 		May 22<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n [Verilog] Beginner's guide to RTL design using Xilinx\/Vivado tools<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n June 2nd (Tuesday) -
Wednesday, June 3rd<\/td>\n 		May 22<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Zynq SoC Embedded System Development<\/a>\n <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Thursday, May 28th -
Friday, May 29th<\/td>\n 		May 19<\/td>\n \n Now accepting applications\n <\/td>\n <\/tr>\n\n \n
\n Creating a color bar generator circuit using ZYBO <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Wednesday, May 27th<\/td>\n May 18<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n
\n Design Closure Technique Design & Power <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Tuesday, May 26th<\/td>\n May 15th<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n
\n PCI Express Designs <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Thursday, May 21st -
Friday, May 22nd<\/td>\n 		May 12<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n
\n Embedded Heterogeneous Design <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n May 19th (Tuesday) -
Wednesday, May 20th<\/td>\n 		May 8th<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n
\n Timing Closure in the Vivado Design Suite <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n May 19th (Tuesday)<\/td>\n May 8th<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n
\n Timing Constraints and Analysis in the Vivado Design Suite <\/td>\n \n
\n \"\"\n <\/div>\n \n <\/td>\n
FPGA<\/td>\n Monday, May 18th<\/td>\n May 7th<\/td>\n \n Registration closed\n <\/td>\n <\/tr>\n\n \n \n <\/tbody>\n<\/table>\n\n<\/div><\/div>\n\n\n\n

Past Seminars<\/h3>\n\n\n\n
\n \n \n \n
title<\/th>\n Company Name<\/th>\n category<\/th>\n Date<\/th>\n Closing date<\/th>\n Reception status<\/th>\n <\/tr>\n\n \n\n
There is currently no event information<\/td>\n <\/tr>\n\n <\/tbody>\n<\/table>\n\n<\/div><\/div>","protected":false},"excerpt":{"rendered":"

External Seminars We provide information on external seminars held by manufacturers we deal with. Information that is useful for hardware and software developers [\u2026]<\/p>","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"page-seminar.php","meta":{"_acf_changed":false,"_editorskit_title_hidden":false,"_editorskit_reading_time":0,"_editorskit_is_block_options_detached":false,"_editorskit_block_options_position":"{}","om_disable_all_campaigns":false,"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"class_list":["post-5471","page","type-page","status-publish","hentry"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/pages\/5471"}],"collection":[{"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/comments?post=5471"}],"version-history":[{"count":44,"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/pages\/5471\/revisions"}],"predecessor-version":[{"id":8323,"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/pages\/5471\/revisions\/8323"}],"wp:attachment":[{"href":"https:\/\/shinko-sj.co.jp\/en\/wp-json\/wp\/v2\/media?parent=5471"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}