External seminar information

External Seminars

We will provide you with information on external seminars held by manufacturers that we deal with. We provide useful information for hardware and software developers, so please feel free to register and participate.

Seminar Overview

For customers who want to obtain product information, select products, or learn development methods, we will solve your development problems through on-site training and online seminars.

Upcoming Events

title	Company Name	category	Date	Closing date	Reception status
Armadillo Base OS Basic Seminar		Embedded CPU Board	Manufacturer On the homepage Please check.		Now accepting applications
Software and hardware system design seminar		FPGA	December 23rd (Tue) - Wednesday, December 24th	December 12	Now accepting applications
Timing Closure Techniques Part 2		FPGA	December 23 (Tuesday)	December 12	Now accepting applications
Timing Closure Techniques Part 1		FPGA	Monday, December 22nd	December 11	Now accepting applications
Design Closure Technique Design & Power		FPGA	December 18th (Thursday)	December 9	Now accepting applications
Versal Adaptive SoC: Network on Chip		FPGA	Wednesday, December 17th	December 8	Now accepting applications
Zynq SoC Embedded System Development		FPGA	December 16th (Tue) - Wednesday, December 17th	December 5th	Now accepting applications
Migrating to the Vitis Unified IDE		FPGA	December 16th (Tuesday)	December 5th	Now accepting applications
Introduction to MicroBlaze-v development using ARTY		FPGA	Monday, December 15th	December 4th	Now accepting applications
[VHDL] First RTL design using Xilinx/Vivado tools		FPGA	December 11th (Thursday) - December 12th (Friday)	December 2nd	Now accepting applications
Versal Adaptive SoC: Design Methodology Part 2		FPGA	December 12th (Friday)	December 3	Now accepting applications
Versal Adaptive SoC: Design Methodology Part 1		FPGA	Wednesday, December 10th - December 11th (Thursday)	December 1st	Now accepting applications
Introduction to Artix-7 FPGA Design and Development using Vivado Design Suite		FPGA	December 12th (Friday)	December 3	Now accepting applications
Debugging with Vivado Logic Analyzer: Basics		FPGA	December 11th (Thursday)	December 2nd	Now accepting applications
Creating a color bar generator circuit using ZYBO			0/00 (*)	0/00	Now accepting applications
Versal Adaptive SoC: Architecture		FPGA	December 8th (Monday) - December 9th (Tuesday)	November 27	Now accepting applications
Versal adaptive SoC: Quick Start		FPGA	December 4th (Thursday)	November 25	Now accepting applications
Zynq SoC System Architecture		FPGA	December 2nd (Tue) - Wednesday, December 3rd	November 20	Registration closed
Verification with SystemVerilog		FPGA	December 2nd (Tue) - Wednesday, December 3rd	November 20	Registration closed
FPGA design implementation with Vivado Design Suite		FPGA	December 2nd (Tue) - Wednesday, December 3rd	November 20	Registration closed
Embedded Systems Software Design OS		FPGA	November 28th (Friday)	November 18	Registration closed
Embedded Systems Software Design Basic		FPGA	Wednesday, November 26th - November 27th (Thursday)	November 14	Registration closed
Zynq UltraScale+ MPSoC Hardware Design		FPGA	November 25th (Tue) - Wednesday, November 26th	November 13	Registration closed
Versal AI Engine 3: Kernel Programming and Optimization		FPGA	November 20th (Thursday) - November 21st (Friday)	November 11	Registration closed
PCI Express Designs		FPGA	November 20th (Thursday) - November 21st (Friday)	November 11	Registration closed
[Verilog] Beginner's guide to RTL design using Xilinx/Vivado tools		FPGA	November 18th (Tue) - Wednesday, November 19th	November 7	Registration closed
Spartan UltraScale+ FPGA: Architecture		FPGA	November 17th (Monday) - November 18th (Tuesday)	November 6	Registration closed
Versal Gen2 Architecture		FPGA	November 13th (Thursday) - November 14th (Friday)	November 14	Registration closed
Vivado Design Suite Tool Flow		FPGA	November 13th (Thursday)	November 4th	Registration closed
Embedded Heterogeneous Design		FPGA	November 11th (Tue) - Wednesday, November 12th	October 30	Registration closed
Software and hardware design and implementation seminar		FPGA	November 11th (Tuesday)	October 30	Registration closed
Timing Closure in the Vivado Design Suite		FPGA	November 7th (Friday)	October 28	Registration closed
Timing Constraints and Analysis in the Vivado Design Suite		FPGA	November 6th (Thursday)	October 27	Registration closed
Kria KV260 Vision AI		FPGA	November 6th (Thursday) - November 7th (Friday)	October 27	Registration closed
Getting started with Kria KV260		FPGA	Wednesday, November 5th	October 24th	Registration closed
Designing with SystemVerilog		FPGA	November 4th (Tue) - Wednesday, November 5th	October 23	Registration closed

Past Seminars